Solution
One of the main causes of this delay is if the Analog Output task has to switch its reference clock multiple times per run of the VI. If there is not a reference clock specified when performing a function such as a DAQmx Write, then the default value for the reference clock source will be the internal clock. If later in the code the reference clock is set to another value, such as the PXIe_Clk100 during synchronization, then this delays the VI. Below are two examples one where the reference clock source is set beforehand, so there is less delay and one where the reference clock is not set so the Phase Lock Loop has to reset:
Slow VI:

Faster VI: