Unable To Build FPGA VI After Grouping Controls in Arrays

Updated Oct 25, 2018

Reported In

Software

  • LabVIEW FPGA Module

Issue Details

When developing my FPGA VI, it appears that clusters and arrays are using more slices than they should, and the build fails after a long time. Why is that ?

Solution

Even if it is easier for the developper to group similar data items in arrays, it is not recommended to do so when designing a FPGA VI, as arrays add implementation constraints and might cause an already complex mapping process to fail due to excessive constraints. In order to correct these issues, consider splitting your arrays into smaller ones, or ideally remove them completely. You can also use DMA FIFOs and interleaving to communicate with the FPGA VI, and store the data in memory blocks. For more information about interleaving, check out this article : Transferring Multi-Channel Data in DMA Applications (FPGA Module)

Additional Information


When you place a cluster or array on the front panel of your main LabVIEW FPGA VI, the resulting LabVIEW implementation includes support for the FPGA Interface. The FPGA interface enables your host VI to read from or write to the cluster or array. When the total size of the cluster or array is less than or equal to 32 bits, each bit is represented by 1 flip-flop.

The total size is equal to the number of bits per element times the number of elements. For example, an array with 4 U8 elements has a total size of 32 bits. When the total size of the cluster or array exceeds 32 bits, double buffering is implemented in order to provide access protection for the FPGA Interface. The consequence of double buffering is that each bit of the cluster or array requires 2 flip-flops instead of one.

For clusters and arrays, the FPGA Interface must implement the following behind the scenes:
  1. Access Protection: All elements of the cluster or array must be accessed as a unit. For example, if the host VI reads a cluster, and at the same time the FPGA VI is writing to that cluster, the host VI must wait for the FPGA VI to complete its write. If this sort of protection did not exist, the host VI could read some cluster elements as old data before the FPGA VI write finished, and the remaining elements as new data.
  2. Flatten/Unflatten: Since the FPGA VI and the host VI may use different conventions to store clusters and arrays, the data must be flattened before transfer, and unflattened after transfer. This flatten/unflatten process is similar to the mechanism LabVIEW uses for file I/O. For more information on this topic in LabVIEW 7.1 or earlier, refer to the LabVIEW Data Storage application note in the LabVIEW Bookshelf. In LabVIEW 8.0 or later, refer to the How LabVIEW Stores Data in Memory book (linked below) in the LabVIEW Help.
These implementation issues are simple for data types such as integers, but for clusters and arrays the overhead involved can increase significantly. On the FPGA VI side, code for clusters or arrays can require a a significant number of FPGA gates which reduced the available space for other items in the VI. On the host side code to flatten/unflatten consumes processor time, which can result in reduced performance. In addition to the front panel of your main LabVIEW FPGA VI, these conditions also apply to using clusters or arrays as global variables within LabVIEW FPGA.

For more information on the definitions of logic cells, logic slices, and configurable logic blocks and gates, refer to What is the Definition of Logic Cells, Logic Slices, Configurable Logic Blocks and Gates in Regards to FPGA Devices?