Can I Run an FPGA VI Faster Than an I/O Module Can Sample?

Updated Dec 7, 2018

Reported In


  • CompactRIO Chassis
  • CompactRIO Controller


  • LabVIEW FPGA Module

Issue Details

I am working with a cRIO chassis along with an input module. I have configured my FPGA code to execute at a rate that is faster than what my input module (or reconfigurable card) can support. What behavior can I expect to see from this application?


The code will not run any faster than the maximum sample rate of the slowest input module. You will not receive errors or warnings that the code is attempting to poll an FPGA I/O Node faster than data can be retrieved. Rather, each time the loop encounters the I/O Node, the code will pause until the data is available from the input module.

This concept can be illustrated in the example below. The loop in the FPGA code shown below is configured to run at 500kHz (2us delay each loop iteration). However, setting this delay will not guarantee that the code will run at this rate. Assuming that AI0- AI3 are taken from a cRIO-9215 module, the maximum loop rate achieved will be 100kHz. This is limited by the maximum sample rate of the cRIO-9215; according to the Operating Instructions for this module (linked below), the maximum sample rate is 100kHz.


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