How Do I Synchronize Data Transfer from FPGA to RT with DMA FIFOs?

Updated May 16, 2023

Reported In


  • CompactRIO Chassis


  • LabVIEW FPGA Module
  • LabVIEW Real-Time Module
  • LabVIEW

Issue Details

I am reading from multiple channels on my cRIO and would like to send all of this data to my RT host to be processed, but want to make sure that all of the data is synchronized. How can I do this?


As long as your are reading from each FIFO at the same rate, your data will automatically be synchronized.

Additional Information

Depending on your controller, you will have a specified limited number of DMA FIFOs available. If you are sampling from more channels than you have FIFOs or have limited resource space and would like to use fewer FIFOs on your FPGA, you can have multiple channels written to one DMA FIFO using interleaving.