As long as your are reading from each FIFO at the same rate, your data will automatically be synchronized.
Depending on your controller, you will have a specified limited number of DMA FIFOs available. If you are sampling from more channels than you have FIFOs or have limited resource space and would like to use fewer FIFOs on your FPGA, you can have multiple channels written to one DMA FIFO using interleaving.
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