When I Compile My FPGA VI I Get an Error About nirviGetConfiguredClocks.VI

Updated Aug 9, 2022

Reported In

Software

  • LabVIEW FPGA Module

Issue Details

When I try to compile my FPGA VI, I get the following error:

An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information:

nirviRequestAResetCyclesForCLIP.vi<-nirviGetVitalTSInfoForBackend.vi<-nirviGetConfiguredClocks.vi<-nirviGetConfiguredClocks.vi.ProxyCaller

Solution

This error indicates that a clock signal has been instantiated, but no clock was actually connected to it. To solve you need to change your clock settings by following the next steps:
  1. Right click FPGA>>New FPGA Base Clock.
  2. Add the Clock for the frequency you need (200 MHz for example).
  3. Go to the properties of the IO Module.
  4. Go to Clock Selections.
  5. Select the clock that you created on step one (the 200 MHz clock for this example).

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