Bit Shift in FPGA Digital I/O Loopback Test

Updated Sep 27, 2018

Reported In

Hardware

  • PXI-7811
  • PXIe-7846

Software

  • LabVIEW FPGA Module

Issue Details

I am writing bits to a digital output channels on a R series card to perform digital communication (such as SPI). I have connected the digital output to a digital input to perform a loopback test, but the data that I am reading back appears to be bit-shifted by 1 bit. How do I fix this?

Solution

Change the number of Synchronization Registers on the FPGA IO Advanced Code Generation to 0 for read.
  1. In the project explorer locate the FPGA I/O items
  2. Right click the FPGA I/O item >> Properties >> Advanced Code Generation
  3. Change number of Synchronizing Registers for Read to 0
  4. Ensure that in the FPGA code the FPGA I/O nodes' properties are set to 'Inherit from Project'.

Additional Information

This happens due to different number of synchronization (sync) registers used by digital output and digital input. The default number of synchronization registers for output is one because all signals being output are synchronous to the FPGA clock used for the loop. Thus, we can guarantee the data latched by those flip flops is in a valid and stable state.

For input (read), we assume the signal coming in is from the outside world, asynchronous to our FPGA base clock, which means it is possible that during the process of the flip flops latching data, the input could be metastable (i.e. not 0 or 1). By adding a second sync register, we provide more time for the signal to settle to a valid value before being passed to the code in the block diagram. 

For a loopback, we can either change the number of sync registers on the input to 0 or 1 or count the loop iterations and only begin processing the data when the first bit would have reached the second sync register (third loop iteration).

In SPI communication we know when the data is available and stable as it is clocked by the master device so we can use 0 as the number of input registers to read.

More information on the FPGA synchronization registers can be found in the related links section below.

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