Why Is My Slow Sampled C Series Module Able to Operate at a Higher Sampling Rate Than the Specified Maximum Rate?

Updated Aug 31, 2018

Reported In

Hardware

  • NI-9211
  • NI-9219
  • cDAQ-9171
  • cDAQ-9174

Issue Details

I have a slow sampled cDAQ device in a multi-slot chassis. Why am I not receiving an error when this device acquires data at a rate faster than its maximum sampling frequency specification? When I place the module in the single slot chassis, I'm only able to acquire data at the maximum sampling frequency specification.

Solution

A slow sampled cDAQ device is one with a slow sampled ADC. This type of ADC can operate in two timing modes: high resolution and high speed. High resolution mode optimizes accuracy and noise rejection whereas high speed mode optimizes sample rate and signal bandwidth. For each slow sampled device, there is a sampling rate threshold that differentiates the high resolution and high speed modes.


When a slow sampled cDAQ device is in a single-slot chassis, DAQmx will automatically switch timing modes when the sampling rate threshold is reached. By contrast, in a multi-slot chassis, high resolution mode will always be the default. If you request a sampling rate that is higher than the maximum sampling rate for high resolution mode (without explicitly changing the timing mode), DAQmx will remain in high resolution mode and create duplicate samples.

When a slow sampled device is grouped with another device in a task in a multi-slot chassis, the system will operate at the requested sampling rate, even if this rate is above the maximum sampling rate specified for the slow sampled device. However, the slow sampled device will only acquire new data at its maximum sampling rate, where all other data points will be replicated from the previous sample. The device is not able to sample at a faster rate than its specification even though it is operating, by replicating data, at a faster rate.


This ability to replicate data is supported only by multi-slot cDAQ chassis. So, a slow sampled cDAQ device in a single-slot chassis will not be able to operate at a sampling rate faster than its specification. The purpose of this replication process is to support synchronization between a slow sampled module and another module that can sample faster. Because there is not a need to synchronize modules in a single-slot chassis, there is no need for a single-slot chassis to produce duplicate samples.
 

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