Why Do I Have a Delay Between My AI and AO on LabVIEW FPGA ?

Updated Sep 28, 2018

Issue Details

I am acquiring a signal with an Analog Input module, and redirecting it directly to the Analog Output module via the I/O node on LabVIEW FPGA.
I have benchmarked the loop duration of my While Loop, and the delay is way bigger than the loop period duration.
How is it possible ?


The reason why you are seeing this is probably because you are using a module with a Delta-Sigma ADC.
Delta-Sigma ADC always have an input delay between the first analog acquired point, and the first available data due to its nature.
This delay is called Input Delay and can be calculated thanks to the specifications document of the module.
For example, a NI-9250 has an input delay of :

For a sampling frequency of 102.400kS/s, the module will then have a delay of 333.3µs + 2.7µs.


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