Error -307727 When Setting up a Counter Output Task with Counter/Timer Module in VeriStand

Updated Oct 26, 2020

Reported In


  • PXIe-6612
  • PCIe-6612
  • PXI Counter/Timer Module


  • VeriStand

Issue Details

I am trying to set up a counter output task in my VeriStand project using an Counter/Timer Module card, but see error -307727 when I try to deploy the project.
What is wrong with the timing source in my project?


You need to change the True to False at the Enable HWTSP in the diagram.
  1. Right click on the Counter/Timer Module card and select Add Channels.
  2. Select channel type to add >> select CO
  3. Channel Properties>>Enable HWTSP>>False

Additional Information

NI VeriStand limits how quickly you can update the frequency and duty cycle values that define the pulses it generates. At least one complete pulse must elapse with a set of frequency and duty cycle values before you can change one of these values. Otherwise, if you update a value too quickly, NI VeriStand reacts in one of the following ways:
  • If the Enable HWTSP property is False, meaning the pulse generation uses implicit timing, NI VeriStand ignores the new value and continues using the latest value you successfully set. 
  • If Enable HWTSP is True, meaning the pulse generation uses hardware-timed single-point sampling mode, NI VeriStand returns an error. 
Typically, implicit timing is appropriate when the measurement does not require sample timing, such as with counters for buffered frequency measurement, buffered period measurement, or pulse train generation.