Loop Speed Decreases When Using the AI/AO Nodes of a USB R Series Device

Updated Sep 28, 2020

Reported In


  • USB-7856
  • USB-7845
  • USB-7855
  • USB-7846


  • LabVIEW
  • LabVIEW FPGA Module


  • NI-RIO 13.0

Issue Details

Depending on how I configure the block diagram of the FPGA for my USB R Series I get different loop times. In the below configuration my FPGA VI is only capable of running at 41 ticks of a 40 MHz base clock. The USB R Series device is specified to be able to run at 1MHz, 40 ticks of a 40 MHz base clock.
I want to ensure that I can run the node at the fastest rate possible. How do I accomplish this?


To ensure we can execute at 40 ticks of a 40MHz Clock remove the error terminals from the IO Node, remove the 

Loop timer. vi, or compile at a faster rate (80MHz). The below image depicts how to implement the first two solutions.