PXI-6683 IRIG-B Input Considerations

Updated Apr 18, 2018

Reported In


  • PXI-6683
  • PXI-668XH


  • NI-Sync

Issue Details

I plan to use the PXI-6683 to input an IRIG-B DC signal from a masterclock.  Whenever I first start the masterclock, however, it defaults to a SMPTE timecode signal and must be configured for IRIG-B DC.  Will a SMPTE timecode signal damage the PXI-6683 if connected to PFI0 for a short time while configured for IRIG-B DC?


As long the signal which is connected to PFI0 is within the input voltage specifications for the PXI-6683 when configured for IRIG-B DC, you will not damage the device. 

When powering up the PXI-6683, PFI0 is configured as an IRIG-B AM input, and can tolerate voltages from -5 V to +5 V.  After being configured for IRIG-B DC, a solid-state relay is closed allowing digital operations.  This will limit the input tolerance to -0.5 V to +6.0 V.  Supplying a voltage outside this range can damage the device circuitry.


Not Helpful