FPGA Digital I/O Delays

Updated Mar 26, 2018

Reported In

Software

  • LabVIEW FPGA Module

Issue Details

Why does my FPGA Digital Output have delay when connected directly to a Digital Input on my block diagram?

Solution

Your block diagram may resemble Figure 1:
It is likely you are observing behavior similar to Figure 2:

The blue line represents the averaged input pin level and the red line is the averaged output pin level. As you can see, the delay between the input exceeding the logic high threshold and the output responding is about 50ns. Propagation delay from cabling is responsible for 10ns of this delay.

LabVIEW FPGA Synchronization registers account for the remaining 40ns of delay. LabVIEW places these synchronization registers in between the FPGA hardware I/O interface and the FPGA I/O node.  Synchronization registers execute in one clock cycle.

Additional Information

Why use synchronization registers?

The registers ensure that input and output data meet timing constraints. If a logic high on an input occurs near the end of a clock cycle, then it gets clocked into the register for one cycle and presented to your code at the very beginning of the next clock cycle. This allows the data to propagate through all the logic within 1 clock cycle.  By default, LabVIEW uses 2 registers for input and 2 for output.

What happens if I set the synchronization register value to 0?

You can modify the number of synchronization registers for I/O data in the FPGA I/O Properties dialog box, as described in the FPGA I/O Properties Dialog Box Help.

Figure 3 illustrates what happened in a test setup with the synchronization register value set to 0:

In this case the input signal was a pulse train created on the same FPGA, so it was synchronized with the FPGA logic. Therefore we did not encounter any issues with metastability. The 10ns delay is due to lengthy cabling.

Set your Number of Synchronizing Registers for Output Data to 0 only if you also use the HDL Interface Node or component-level IP (CLIP), and the HDL code contains its own synchronization registers. Otherwise, you might introduce metastable data in the FPGA VI and experience unpredictable behavior. This metastability happens because the there is not always enough time to process the input signal and then create an output signal. If you received an input signal near the end of the clock cycle, the output would not resolve in time and you would get effectively random data on the output. That is why the synchronization registers are important.

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