How Do I Set the Rate of a Timed Loop on an FPGA Target?

Updated Jul 12, 2019

Reported In

Software

  • LabVIEW FPGA Module
  • LabVIEW Real-Time Module

Issue Details

My FPGA code contains a Timed Loop structure. I've wired 100 ticks to the Period (dt) of my loop.  However, when I compile and run my FPGA code, the loop seems to run at a full 40MHz without waiting the 100 ticks between loop cycles like I specified.  Why is this happening?

Solution

On an FPGA Target, the Timed Loop structure can only run as a single cycle Timed Loop. The only parameter that matters is the Source Name.  The Source Name defaults to the 40MHz FPGA clock, but can be configured to use a derived clock.  The compiler ignores every other parameter.  


If you want to implement other custom timing options, you can use a While Loop with either a Loop Timer, Wait function, or Sequence structure.  Examples of these implementations are shown below, and can also be seen in the FPGA Module Help in the Related Links section.