Configuring an External Clock in a CLIP

Updated Apr 6, 2023

Reported In


  • PXI FPGA Module for FlexRIO


  • LabVIEW FPGA Module

Issue Details

I have configured a user defined CLIP, when I route a internal clock it executes fine but when I route an external clock, it is not executing.


For CLIPs to run on a external clock, a dedicated line for the clock has to be configured. For instance we are using a simple adder which is clocked using the "clk" signal.

1. As shown below configure the "clk" signal as a clock line in the signal type.

2. Refer to the link CLIP Tutorial, Part 3: Adding CLIP to a Project , as mentioned in the step 9, configure the external clock line in the Clock selection page .


Additional Information

For complete information on configuring the CLIPs and adding them to the project refer to the CLIP Tutorial . For highly detailed information on using the LabVIEW FPGA Module and its features refer to the comprehensive LabVIEW FPGA Module Help Document