Error -63043 in LabVIEW FPGA When Reading Data

Updated Feb 7, 2024

Reported In


  • CompactRIO Chassis


  • LabVIEW
  • LabVIEW FPGA Module
  • LabVIEW Real-Time Module

Issue Details

  • My FPGA code runs for a few seconds, then disconnects with the following error.
  • I am trying to read data from my FPGA using either the FIFO Read or the FPGA Read method. I get the following error.

Error -63043: The session is invalid. The target may have been reset or rebooted, or the network connection may have timed out because of processor overuse. Check the network connection, reduce the demand on the processor, and decrease the timeout of the operation that failed. 

Why is this issue happening, and how can I resolve it?


This issue will arise because the host program thinks that the FPGA has been disconnected, which may be due to any of the following causes:
  • The physical connection (Ethernet) between the host and the FPGA has been compromised. Check your connection or try a different Ethernet cable. 
  • If you are referencing your FPGA resource as rio://X.X.X.X/RIO0 and you are trying to run without a network connection using RIO0 instead of rio://X.X.X.X/RIO0 in order to reference the FPGA locally and not its network location.
  • This can happen if you close the project while the RIO is running. Before closing the project, LabVIEW generates a request to disconnect RIO. After accepting the request, if you start a LabVIEW project (while you have your  RIO running) you may see this error. To make the project start working again, you will need to reboot RIO. 
  • We aren't receiving data from the FPGA, or aren't receiving enough data to fill the FIFO, leading to a timeout. Make sure that the data is actually being acquired on the FPGA side (we can do this by running the FPGA in Interactive Mode, i.e. just pressing 'Run' on the FPGA VI).
  • The processor may be overused. You can monitor this by using the NI Distributed System Manager and looking for your device.
  • The timeout of the operation has failed; decrease it by following the steps shown in this article.
  • If using a cRIO chassis, check your power supply is providing enough current to the hardware. In some cases, when calling the FPGA bitfile there will be an initial spike in the chassis power consumption, if the power supply limit is surpassed the chassis will reboot resulting in loss of communication.