I have a CompactRIO (cRIO) set up such that some of my modules are utilizing Scan Mode and some of my modules have custom code written in an FPGA VI. My project looks similar to the one pictured below with some modules under the Real-Time (RT) Target and some modules under the FPGA Target. The custom code for my FPGA VI is very simple but the compile time is much longer than I would have expected. Why does it take so long to compile the FPGA code?
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