In the project configuration you have modules that will utilize both the RIO Scan Engine and FPGA mode. Therefore, the FPGA bit file will need to incorporate both of these elements. The result of your compilation is a single bitfile that supports the Scan Mode features for modules configured to use Scan Mode as well as your custom FPGA logic that communicates directly with the remaining I/O modules.
During an FPGA compile, LabVIEW performs a great deal of optimization to reduce digital logic and create an optimal implementation of the LabVIEW application. Behind the scenes, your graphical code is translated to text-based VHDL code. Then industry standard Xilinx ISE compiler tools are invoked and the VHDL code is optimized, reduced, and synthesized into a hardware circuit realization of your LabVIEW design.
This configuration with modules under the RT target (utilizing the RIO Scan Interface Framework) and under the FPGA target is known as hybrid mode. It is important to note that when in this Hybrid Mode, the RIO Scan Engine will still utilize two of your DMA (Direct Memory Access)
channels. These DMA channels are reserved and will not be available for use in your FPGA code.
To learn how to setup Hybrid Mode, please see this Knowledge Base How Can I Use Scan Engine and FPGA Simultaneously on a CompactRIO (Hybrid Mode)?
Learn about different options for compiling FPGA code as well as how to compile faster in Compile Faster with the LabVIEW Compile Cloud Service