Solution
Note: The Convert Clock rate is the inverse of interchannel delay, for example a Convert (Channel) Clock rate of 80,000 Hz corresponds to an interchannel delay of 12.5 µs.
Note: Padding time is applied by the NI-DAQmx driver only when acquiring multiple channels on multiplexed devices. For single-channel acquisitions on multiplexed devices, or when using simultaneous-sampling devices, no ADC settling time is required.
How the Convert Clock rate is chosen
The Convert Clock is determined differently depending on the version of the driver you are using.
Above this rate, the convert clock runs at the aggregate sample rate, and no extra padding time can be inserted.
This limit depends on the device’s maximum conversion rate. For example, the PCI-6250 supports 1 MS/s conversions (1 µs conversion time), so adding the same 10 µs settling delay results in an 11 µs convert period, equivalent to a Convert Clock rate of approximately 90.9 kS/s.
Providing sufficient settling time is important for measurement accuracy. On the PCI-6220, achieving ±1 LSB accuracy requires at least 7 µs of amplifier settling time. Higher source impedance can further increase the required settling time.
- NI-DAQmx 7.0 to 7.3
In these versions, the Convert Clock is always chosen to absolutely maximize amplifier settling time. Interchannel delay is simply the time between samples divided by the number of channels. The Convert Clock, then, is simply the Sample Clock rate multiplied by the number of channels being acquired. This is illustrated in the image below.
- Traditional NI-DAQ (Legacy)
By default the Traditional NI-DAQ driver chooses the fastest Channel Clock rate possible while still allowing extra time for adequate amplifier settling time. At slower scan rates, 10 µs of delay is added to the fastest possible channel conversion rate of the board (the same as the maximum scan rate) to derive the Channel Clock. This is illustrated in the image below.
As the scan rate increases, there comes a point where there is not enough time for a full 10 µs of additional delay time between channel conversions and still finish acquiring all channels before the next edge of the Scan Clock. At this point, the driver simply uses round robin channel sampling, evenly dividing the time between scans by the number of channels being acquired to obtain the interchannel delay. In this case the Channel Clock can be calculated by simply multiplying the scan rate by the number of channels being acquired.
Overriding the default Convert (Channel) Clock with your own rateThere may be special cases when you want to override the default Convert Clock rate and specify your own rate. For example, you may want to increase interchannel delay to maximize amplifier settling time because you have a high source impedance. Conversely, you may want to decrease interchannel delay as much as possible in order to achieve a more "simultaneous" acquisition of channels (sacrificing accuracy due to decreased amplifier settling time).
- NI-DAQmx
Using NI-DAQmx, you can manually set your Convert Clock rate using the AIConv.Rate property in the DAQmx Timing property node. The VI below shows how this is done.
- Function Calls
If you are using function calls, you can get/set/reset the Convert Clock using the following function calls: DAQmxGetAIConvRate, DAQmxSetAIConvRate, DAQmxResetAIConvRate.
- Traditional NI-DAQ (Legacy)
Using Traditional NI-DAQ, you can set your Channel Clock rate manually with the interchannel delay input of the AI Config VI, which calls the Advanced AI Clock Config VI to configure the channel clock. This overrides the default Channel Clock rate.
SCXI - NI-DAQmx 8.5 and greaterStarting in NI-DAQmx 8.5, a total delay of 20 µs was added to the fastest possible channel conversion period on an SCXI chassis connected to a 16-bit or 18-bit E or M Series device. If a sample rate is set fast enough to require a convert clock rate greater than the default rate, warning 200011 is generated, informing the user that the accuracy of the measurement might be compromised. However, since this is a warning, the convert clock used is based on the rate needed by the sample clock set by the user (that is, convert clock = sample clock * number of channels).
For SCXI chassis containing a module with track-and-hold circuitry, 10 µs of padding is now added to the fastest possible conversion rate when connected to a 12-bit E Series device.
These changes ensure the most accurate data is being acquired by maximizing the settling time between each channel. However, if the effect on the performance due to this change is too great (such as on an RT system using Hardware Timed Single Point in a control loop), then the convert clock rate attribute can be explicitly set, overriding the default rate.
To calculate the fastest sample rate where no accuracy is lost due to settling time (and no warning is thrown), use the following formula: Sample Rate = 1 / (0.000020 * Number_of_Channels). If you need to run your application at a faster sample rate, check the user manual of your SCXI module to get the "minimum scan interval" accuracy specifications.
This change affects only multichannel acquisitions. In NI-DAQmx 8.4 and earlier, only 10 µs of delay was added to the fastest possible channel conversion rate on an SCXI chassis without a track-and-hold module connected to any DAQ device. In these versions of NI-DAQmx, no warning is generated when the sample rate needed a faster convert clock than was chosen by default. When an SCXI chassis with a track-and-hold module was present, the convert clock rate selected was the fastest possible rate that the DAQ device can handle, up to 333kHz.