Unable to Simulate FPGA VI that Calls Vision Functions

Updated Feb 5, 2018

Reported In


  • NI-1483
  • PCIe-1473
  • CompactRIO Chassis
  • Industrial Controller
  • PXI FPGA Module for FlexRIO


  • LabVIEW FPGA Module
  • Vision Development Module

Issue Details

I have an FPGA VI that is performing some image processing using the Vision Development Module FPGA functions. I don't have my FPGA hardware yet, so I am trying to run the VI in Simulation Mode to verify that it is working correctly. However, when I run the VI, I get an error:

Error occurred in IP Integration Node:

Possible reason(s):
Undefined error. If this error persists, contact National Instruments technical support.


To run your FPGA VI in simulation mode, you will need to the IP Integration Node (IPIN) support files. To do this:
  1. If not installed already, install the local Xilinx Compile Tools compatible with your FPGA target from NI's download page.
  2. Navigate to C:\Program Files (x86)\National Instruments\[LabVIEW 20xx]\vi.lib\visionFPGA\IPB.
  3. Open the folder for the FPGA target that you are using. If you don't know which FPGA chip your card uses, you can check this list of NI RIO devices:
    • The K7 folder is for Kintex 7 FPGA devices
    • The Z1 folder is for Zynq FPGA devices.
    • The ISE folder is for Virtex 5 devices.
  4. In that folder, locate the VI associated with the function that you would like to simulate. For example, if I was trying to run the code shown in the following screenshot on a Kintex 7 target, I would open the k7_GM_Erosion_3x3 U8x8.vi from the K7 folder.
  1. With the VI open, go to Tools»FPGA Module»Regenerate IP Integration Node Support Files...
  2. In the Regenerate IP Integration Node Support Files dialog box, make sure the correct Top-level VI path is indicated and that the Regenerate out-of-date support files only checkbox is unchecked.
  3. Click Regenerate Files.
After the files have been generated, you should then be able to run your FPGA VI in simulation mode.

Additional Information

Many of the Vision FPGA functions call into IP Integration Nodes. While these functions will execute on actual FPGA hardware, simulating the FPGA execution requires additional support files. If these support files have not been generated, the error shown above will be thrown and you will not be able to simulate the FPGA execution without regenerating the support files.


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