Run SCTL on FPGA with Multiple Clock Domains

Updated Feb 14, 2018

Reported In


  • LabVIEW FPGA Module
  • LabVIEW Full
  • LabVIEW Professional

Issue Details

I am looking to see if it is possible to change between clock domains while the code is running on the FPGA (external and on-board clock reference). I am curious to see if I can change the clock rate on the FPGA, if the compilation was successful. If I compiled my code at 200 MHz, can I change the clock rate at 40 MHz while the code is running?


The answer to this question is no, but there are two solutions which can help you in achieving this.


  1. Create two different VIs which will generate after compilation two bitfiles. One VI/bitfile for each clocking. At this point you can dynamically choose which to load and run in your host VI. When you change between them, there will be a time in which the FPGA will be reconfigured to the new bitfile. At that time, the FPGA will not be running any code.
  2. Create 2 SCTLs in your FPGA code that run simultaneously (with different clocks). For more information about this, see the below articles.

Transferring Data Among Parallel Loops (FPGA Module)
Implementing Multiple Clock Domains (FPGA Module)

Additional Information

The FPGA is a silicon chip that can be configured using software (LabVIEW -> VHDL). In other words, you use software to programme hardware. Each FPGA has limited resources (I/O blocks, logical blocks, switches) which can be used. For making sure that the code that you wrote can be implemented in hardware (FPGA) the code needs to successfully compile. In the compilation process we take the LabVIEW code, transform it in HDL, then synthesise, map and route it on the FPGA. After this, if the code can be successfully placed on the FPGA, a bitfile is generated, which, from now on, will just load on the FPGA directly without any compilation when called. 

Keeping this in mind, there are two ways through a compilation can fail: 
1.    Resources (not enough resources on the FPGA for the logic we want to implement) 
2.    Timing (the logic took too long to execute) 

When you compile using SCTL, you compile the code using a specific sample rate. Let`s say 40 MHz. If that compiled successfully, you would not be able to change the sample rate on the same code without going again through all the compilation steps. It should be checked that the FPGA can handle that timing. That being said, you can not change the clock while the code is running (inside one VI). And also, you can not load a new bitfile while the code is running. You need to stop the FPGA before implementing the new bitfile. In short, you cannot change the clock on the run. 


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