The 5170R has a
fixed acquisition/sampling rate or ADC clock frequency of 250MS/s. To adjust the sampling rate, You have to change the
DSP decimation factor control available in the
Stream To Host (Host).vi front panel (refer to the below image). The decimation factor is divided by "N" decimation from 250 MS/s where "N" is 16 bit.
You also can create a custom decimation filter. To do that, you will have to modify or replace the existing
integer decimation.vi present in the
Stream To Host (FPGA).vi as shown below.
Additional Information
Decimation Example: If you want to acquire at 10 MHz, the easiest thing to do would be to sample the I/O at 250MHz and then decimate the data by a factor of 25 (i.e. retain one in every 25 data points and discard remaining samples).
External Clock: If you want to use an external clock, please make sure you refer to the specifications in order to provide the correct clock signal to the device. The performance of the PXIe-5170R will be dependent on the quality of the clock source.