NI-Industrial Communications for DeviceNet FPGA API Resource Utilization

Updated Aug 1, 2023

Reported In


  • LabVIEW FPGA Module


  • NI-Industrial Communications for DeviceNet


Hardware : cRIO, sbRIO

Issue Details

As with any FPGA application resource utilization is a major concern. I have noticed that including the DeviceNet FPGA API in my FPGA VI significantly increased the number of resources required to compile the VI. What kind of resource utilization should I expect when working with the API, and how can I determine whether the NI-Industrial Communications for DeviceNet FPGA API will successfully compile on my CompactRIO, Single-Board RIO, or Expansion Chassis?


In order to provide a baseline for resource utilization that you can expect when working with the NI-Industrial Communications for DeviceNet FPGA API, NI has compiled the following list of resource utilization statistics sorted by FPGA target. Due to different hardware or software versions or revisions, your own application might use more or less resources compared with the resource percentage in the following table. 

The statistics, including the amount of LUTs and multipliers, were determined by compiling a standard application built with the DeviceNet FPGA API for each of the different FPGA targets.The application utilized is attached at the end of this document for your reference. Slight variations to the application were made in order to account for architectural differences among various FPGA chip groups, but the main application logic remained the same throughout testing. 
The NI-Industrial Communications for DeviceNet FPGA API is accessible in the NI-Industrial Communications for DeviceNet software 2.3 or later. You can download the software from

Resource Utilization Statistics:
Xilinx FPGA ChipNI-RIO DeviceResource TypeApplication Resource Percentage
Virtex-II, XC2VcRIO-9101; 
Total: 5120Insufficient FPGA Resource*
Regs: 10240
LUTs: 10240
DSP48s: 40
Block: 40
Virtex-5, LX30cRIO-9111; 
Total: 4800Insufficient FPGA Resource*
Regs: 19200
LUTs: 19200
DSP48s: 32
Block: 32
Virtex-5, LX50cRIO-9113;
NI 9154
Total: 720090.60%
Reg: 2880057.00%
LUTs: 2880059.60%
DSP48s: 482.10%
Block: 4814.60%
Virtex-5, LX85NI 9155;
NI 9157
Total: 1296058.00%
Regs: 5184031.70%
LUTs: 5184033.10%
DSP48s: 482.10%
Block: 968.30%
Virtex-5, LX110NI-9159;
Total: 1728044.00%
Regs: 6912023.80%
LUTs: 6912024.80%
DSP48s: 641.60%
Block: 1286.20%
Spartan 3, 1 Million GatesbRIO-96X1;
Regs: 15360Insufficient FPGA Resource*
LUTs: 15360
Block: 24
Spartan 3, 2 Million GateNI 9144; NI 9148;
sbRIO-9602; sbRIO-9612;
sbRIO-9632; sbRIO-9642;
cRIO-9073; cRIO-9074
Regs: 4096043.40%
LUTs: 4096056.80%
Block: 4052.50%
Spartan 6, LX 25sbRIO-9623;
Total: 17280Insufficient FPGA Resource*
Regs: 69120
LUTs: 69120
DSP48s: 64
Block: 128
Spartan 6, LX 45NI 9146;
Total: 682290.80%
Regs: 5457632.30%
LUTs: 2728862.20%
DSP48s: 581.70%
Block: 11620.70%
Spartan 6, LX 75cRIO-9081Total: 1166256.90%
Regs: 9329618.60%
LUTs: 4664835.50%
DSP48s: 1320.80%
Block: 17214.00%
Spartan 6, LX 150cRIO-9082Total: 2303828.50%
Regs: 1843049.40%
LUTs: 9215218.10%
DSP48s: 1800.60%
Block: 2689.00%
ZYNQNI 9145, NI 9147, NI 9149;
myRIO-1900, myRIO-1950;
cRIO-9063; cRIO-9064; cRIO-9065; cRIO-9066; cRIO-9067; cRIO-9068;
Total: 1330072.10%
Regs: 10640025.80%
LUTs: 9215249.60%
DSP48s: 1800.50%
Block: 26833.60%
Kintex 7cRIO-903XTotal: 2535025.7%
Regs: 2028009.3%
LUTs: 10140016.3%
DSP48s: 6000.2%
Block: 3254.9%

* NI does not recommend attempting to compile or run applications using the NI-Industrial Communications for DeviceNet FPGA API on these NI-RIO devices as they have very limited FPGA resources available. Only very simple FPGA applications are likely to run successfully on them.