Solution
In order to provide a baseline for resource utilization that you can expect when working with the NI-Industrial Communications for DeviceNet FPGA API, NI has compiled the following list of resource utilization statistics sorted by FPGA target. Due to different hardware or software versions or revisions, your own application might use more or less resources compared with the resource percentage in the following table.
The statistics, including the amount of LUTs and multipliers, were determined by compiling a standard application built with the DeviceNet FPGA API for each of the different FPGA targets.The application utilized is attached at the end of this document for your reference. Slight variations to the application were made in order to account for architectural differences among various FPGA chip groups, but the main application logic remained the same throughout testing.
The NI-Industrial Communications for DeviceNet FPGA API is accessible in the NI-Industrial Communications for DeviceNet software 2.3 or later. You can download the software from
ni.com/drivers.
Resource Utilization Statistics:
| Xilinx FPGA Chip | NI-RIO Device | Resource Type | Application Resource Percentage |
| Virtex-II, XC2V | cRIO-9101;
cRIO-9102;
cRIO-9103;
cRIO-9104 | Total: 5120 | Insufficient FPGA Resource* |
| Regs: 10240 |
| LUTs: 10240 |
| DSP48s: 40 |
| Block: 40 |
| Virtex-5, LX30 | cRIO-9111;
cRIO-9112 | Total: 4800 | Insufficient FPGA Resource* |
| Regs: 19200 |
| LUTs: 19200 |
| DSP48s: 32 |
| Block: 32 |
| Virtex-5, LX50 | cRIO-9113;
cRIO-9114;
NI 9154 | Total: 7200 | 90.60% |
| Reg: 28800 | 57.00% |
| LUTs: 28800 | 59.60% |
| DSP48s: 48 | 2.10% |
| Block: 48 | 14.60% |
| Virtex-5, LX85 | NI 9155;
cRIO-9116;
NI 9157 | Total: 12960 | 58.00% |
| Regs: 51840 | 31.70% |
| LUTs: 51840 | 33.10% |
| DSP48s: 48 | 2.10% |
| Block: 96 | 8.30% |
| Virtex-5, LX110 | NI-9159;
cRIO-9118 | Total: 17280 | 44.00% |
| Regs: 69120 | 23.80% |
| LUTs: 69120 | 24.80% |
| DSP48s: 64 | 1.60% |
| Block: 128 | 6.20% |
| Spartan 3, 1 Million Gate | sbRIO-96X1;
cRIO-9072; | Regs: 15360 | Insufficient FPGA Resource* |
| LUTs: 15360 |
| Block: 24 |
| Spartan 3, 2 Million Gate | NI 9144; NI 9148;
sbRIO-9602; sbRIO-9612;
sbRIO-9632; sbRIO-9642;
cRIO-9073; cRIO-9074 | Regs: 40960 | 43.40% |
| LUTs: 40960 | 56.80% |
| Block: 40 | 52.50% |
| Spartan 6, LX 25 | sbRIO-9623;
cRIO-9075;
sbRIO-9605 | Total: 17280 | Insufficient FPGA Resource* |
| Regs: 69120 |
| LUTs: 69120 |
| DSP48s: 64 |
| Block: 128 |
| Spartan 6, LX 45 | NI 9146;
cRIO-9076;
sbRIO-9606;
sbRIO-9626 | Total: 6822 | 90.80% |
| Regs: 54576 | 32.30% |
| LUTs: 27288 | 62.20% |
| DSP48s: 58 | 1.70% |
| Block: 116 | 20.70% |
| Spartan 6, LX 75 | cRIO-9081 | Total: 11662 | 56.90% |
| Regs: 93296 | 18.60% |
| LUTs: 46648 | 35.50% |
| DSP48s: 132 | 0.80% |
| Block: 172 | 14.00% |
| Spartan 6, LX 150 | cRIO-9082 | Total: 23038 | 28.50% |
| Regs: 184304 | 9.40% |
| LUTs: 92152 | 18.10% |
| DSP48s: 180 | 0.60% |
| Block: 268 | 9.00% |
| ZYNQ | NI 9145, NI 9147, NI 9149;
myRIO-1900, myRIO-1950;
roboRIO;
sbRIO-9651,sbRIO-9607;
cRIO-9063; cRIO-9064; cRIO-9065; cRIO-9066; cRIO-9067; cRIO-9068; | Total: 13300 | 72.10% |
| Regs: 106400 | 25.80% |
| LUTs: 92152 | 49.60% |
| DSP48s: 180 | 0.50% |
| Block: 268 | 33.60% |
| Kintex 7 | cRIO-903X | Total: 25350 | 25.7% |
| Regs: 202800 | 9.3% |
| LUTs: 101400 | 16.3% |
| DSP48s: 600 | 0.2% |
| Block: 325 | 4.9% |
* NI does not recommend attempting to compile or run applications using the NI-Industrial Communications for DeviceNet FPGA API on these NI-RIO devices as they have very limited FPGA resources available. Only very simple FPGA applications are likely to run successfully on them.