PLL Could not Phase-Lock to the External Reference Clock

Updated May 26, 2022

Reported In


  • PXIe-5644
  • PXIe-5665
  • PXIe-5645
  • PXIe-5646
  • PXIe-5820
  • PXIe-5840
  • PXIe-5841
  • PXIe-5830


  • RFmx



Issue Details

I'm trying to open an RFSA or RFmx session with my NI vector signal analyzer (or vector signal transceiver), but I receive the error -1074118630 or error -1074097950 when I open it using either LabVIEW or the soft front panel.

What does this error mean and how do I fix it?


This error is a result of the instrument not being able to phase-lock loop (PLL) to the reference clock. This often occurs when the reference clock signal has degraded to the point where the device's PLL circuitry is not able to get a lock. You can test whether this is the case by trying different reference clock sources.

These devices usually have at least three different reference clock sources that can be selected: Onboard, PXI_Clk, and RefIn. The Onboard reference clock is the internal clock the device has. The PXI_Clk is the reference clock the PXI(e) chassis shares with the instrument through the backplane connection. And the RefIn option routes the clock connected to the REF IN port of the device's front panel to the internal circuit of the instrument.

If changing the reference clock source doesn't fix the error, then the PLL circuitry in the device is probably at fault and might require repair.