Solution
This error is a result of the VSA not being able to phase locked loop (PLL) to the PXI chassis reference clock. This often occurs when the reference clock signal has degraded to the point where the VSAs PLL circuitry is not able to get a lock. You can test whether this is the case by trying the VSA in a different chassis or supplying it with an external reference clock that meets the reference clock specifications.
For example, in the
manual for the PXIe-5668 Timing Configurations, it is noted at the bottom of the page that the PXIe-5653 module, which supplies the local oscillator for the PXIe-5668, has more stringent timing requirements than most PXIe chassis clocks because of the high-performance OCXO onboard the PXIe-5653. This error will then often be a result of trying to use
PXI_Clk as the reference clock for these types of modules that contain higher precision clocks rather than using the module's onboard clock.
If changing the reference clock source doesn't fix the error, then the PLL circuitry in the VSA is probably at fault. Contact NI support for further troubleshooting.