## Solution

Most DAQ devices have two timebase frequencies: 20 MHz and 100 kHz. To achieve the desired sample clock rate for a given task, this master timebase must be divided down. The divisor is always an integer value and the size of the integer is dependent on the model of the data acquisition board.

**For E Series:**
- AI Sample Clock divisor: 24 bits
- AI Convert Clock divisor: 16 bits
- AO Sample Clock divisor: 24 bits

**For M Series and X Series:**
- AI Sample Clock divisor: 32 bits
- AI Convert Clock divisor: 32 bits
- AO Sample Clock divisor: 32 bits

**Note**: X series devices can use a 100 MHz timebase as well as 20 MHz and 100 KHz.