What Sample Rates Is my DAQ Board Actually Capable of Achieving?

Updated Jul 2, 2018

Reported In


  • NI-DAQmx

Issue Details

I know that my DAQ board is only capable of a finite set of sample rates since the sample clock for analog input and analog output tasks is generated by dividing the onboard clock by an integer value.  When I set the sample rate, the actual sample rate achieved may differ slightly, as explained in KnowledgeBase 27R8Q3YF: How Is the Actual Scan Rate Determined When I Specify the Scan Rate for My Data Acquisition?.

How can I determine what sample rates my device is actually capable of achieving?


Most DAQ devices have two timebase frequencies: 20 MHz and 100 kHz.  To achieve the desired sample clock rate for a given task, this master timebase must be divided down.  The divisor is always an integer value and the size of the integer is dependent on the model of the data acquisition board.
For E Series:
AI Sample Clock divisor = 24 bits
AI Convert Clock divisor = 16 bits
AO Sample Clock divisor = 24 bits

For M Series and X Series:
AI Sample Clock divisor = 32 bits
AI Convert Clock divisor = 32 bits
AO Sample Clock divisor = 32 bits

Note: X series devices can use a 100 MHz timebase, as well as 20 MHz and 100KHz.

Additional Information

For example, assume the timebase divisor is a 16-bit integer. This allows the 20 MHz timebase to be used for sample rates of 20 MHz / 216, 20 MHz / (216-1), 20 MHz / (216-2) all the way up to the maximum sample rate of the device.  


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