Solution
This error can be caused by a number of different factors. Most commonly, software incompatibilities and corruptions.
Try the following recommendations to attempt to resolve this error:
- Confirm that you are using a supported OS and LabVIEW version for your compile software.
- Delete the bitfiles and allow them to be regenerated.
- Use the Compile Cloud Service or a compile server farm.
- If a remote compile session does not fix the issue and you have the appropriate Xilinx Compilation Tool installed, try to uninstall the Xilinx Compilation Tool before compiling.
- Ensure your project and VIs are located in the intended location.
- If the file paths are too long, use the Files tab in the LabVIEW project to relocate your files.
- Remove and recreate the build specification.
- Delete and recreate the affected FPGA nodes.
- In your FPGA Build Specification, try checking the box with the option Allow removal of implicit enable signals inside single-cycle Timed Loops.
- Create a new LabVIEW project and add the existing VIs. Try recompiling the FPGA code after doing this.
- Repair or Reinstall
- LabVIEW
- LabVIEW FPGA
- CompactRIO drivers (if RIO devices are being used)
- FlexRIO Drivers (if FlexRIO devices are being used)
- Compilation Tools
- Reinstall software on cRIO(if RIO devices are being used)
- For versions 18 or older
- As a last resource, you can try to reimage your computer to completely clear any software corruption. Please ask your IT administrator for additional support.
Please note that this list of steps is not exhaustive due to the number of possible causes. If the error persists after trying these steps, contact
NI Support.