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The Effect of UART FIFO Sizes on Serial Application Performance

Updated Dec 19, 2023

Reported In


  • RS-232
  • RS-422/RS-485
  • RS-232/422

Issue Details

How Does UART FIFO Sizes Affect Serial Application Performance?


What is a UART and what are its FIFOs? 

A UART (Universal Asynchronous Receiver/Transmitter) is the device that ultimately controls the receive and transmit (read and write) operations performed by a given serial port. In particular, UARTs have dedicated memory in the form of a FIFO structure (first in first out - a queue structure) for each of the receive and transmit operations. 

The purpose of the FIFO structures is to hold data either received from the serial port or to be written to the serial port. Most UARTs allow the size of the FIFO used to be specified in software, you can see how to do so in the KnowledgeBase article linked entitled: Buffer Overflow with Serial Port When Using VISA with Flow Control. Do note there is a maximum size that is limited by the total amount of memory on the UART, but you can specifically define the size to be used. 

Sometimes not every size less than or equal to the maximum can be selected. For example, many RS-232 ports have UARTs that have a maximum FIFO receive buffer size of 14, but only allow 1, 4, 8, and 14 as possible sizes for use. However, the transmit buffer size of many UARTs can often take every integer value from 1 to 16. NI serial devices have UARTs with 128-byte FIFOs, one for each receiver or transmitter.

How do the FIFOs affect performance?

The size of the FIFO buffers determines when the UART interrupts the CPU in order to transfer data between the FIFO and CPU memory (RAM, where applications running on the CPU have access to the data). Therefore, the size of the FIFOs can affect latencies in writing to and reading from the serial port (usually on the order of milliseconds), as well as the overall performance of a given application. 

For example, if you set the receive buffer to 1, the UART will interrupt the processor to transfer a single byte to CPU memory whenever a byte is received. While this will make a given byte available in RAM as soon as possible after arriving at the port, if data is continuously being received at the port, this will cause many interrupts. As a result, more CPU processing is dedicated to those interrupts which can decrease overall performance if other programs are running. Thus, if latencies on the order of a few milliseconds are tolerable for serial operations, it is often beneficial for overall performance to use a larger receive FIFO size. 

Note that an interrupt will occur regularly in order to ensure that even if the receive FIFO size is, for example, 14 bytes, you can receive and have access to data even if only 4 bytes were ever received. Similarly, the transmit FIFO size dictates the number of bytes that can be transferred from RAM to the transmit FIFO at a time. Therefore, if the transmit FIFO size is larger you can reduce latency in transferring large amounts of data by sending more data on each interrupt. 

Additional Information

There is another important factor which contributes to performance at the application level when writes to the serial port (and from RAM to the transmit FIFO in particular), which is discussed in Choosing Between Synchronous and Asynchronous NI-VISA Functions.