Xilinx FPGA compile error when using the Max & Min function with Arrays

Updated Jan 3, 2018

Reported In

Software

  • LabVIEW FPGA Module

Issue Details

I am using the Max & Min function with arrays in the code on my FPGA. When I try to compile, I get the following Xilinx compile error during synthesis:

LabVIEW FPGA: The compilation failed due to a Xilinx error. Details: ERROR:HDLCompiler:432 - "/NIFPGA/jobs/KUdlCjf_Aq5RA47/NiFpgaAG_00000000_ForLoop.vhd" Line 80: Formal <kmintype> has no actual or default value.

How can I fix this so that my code will compile?

Solution

Use one of the two current workarounds for this issue as follows:
  • Connect the output terminals for both the max and min outputs
  • Index the input arrays before feeding them into the Max & Min function

Additional Information

This compilation error is a result of using arrays as the input to the Max & Min function. This is a known issue since LabVIEW FPGA 2012.

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