Why Do I Have a Broken Wire When Passing My FPGA VI Reference Into a SubVI?

Issue Details

When passing an FPGA VI Reference wire into a subVI, the wire that was once solid is now broken.  The error message states that I have connected two terminals of different types, or that I have connected two clusters of different elements. The type of the source is User Defined Refnum and the type of the sink is also User Defined Refnum. How do I fix this?

Solution

SubVIs that use an FPGA reference require that the type of reference match the specific front panel configuration of the FPGA VI. When you change the FPGA front panel configuration you need to change the reference type. You can do this by binding the FPGA host reference to a type definition so any updates will propagate through your subVIs.

If you have multiple FPGA VIs that have the same front panel configuration, you can use the Up Cast VI to reference a more generic FPGA type.  Complete the following steps to bind the reference output of the Open FPGA VI Reference VI to a type definition: 

LabVIEW 2009 or later:

1. For the Open FPGA VI Reference VI: Place a Open FPGA VI Reference VI on the host VI block diagram. Right-click it and select Configure Open FPGA VI Reference from the shortcut menu. In the dialog box that comes up, select Bind FPGA host reference to type definition. In the pop-up, save the control file(.ctl). Select either your bitfile or FPGA VI. Click Ok to close the Configure Open FPGA VI Reference dialog.
2. Ensure that the control was added to the project.
3. Open the subVI, drag two of the new FPGA type definitions from the project to the front panel, and make one of the type definitions a control and the other an indicator.
4. On the block diagram, replace the current FPGA VI Reference In and FPGA VI Reference Out with the type definition control and indicator, respectively.
5. Delete the FPGA VI Reference In and FPGA VI Reference Out.
6. Reconnect the input and output terminals on the front panel of the subVI to the new type definition control and indicator.

LabVIEW 8.6:

1. Right-click the Open FPGA VI Reference VI on the host VI block diagram and select Configure Open FPGA VI Reference from the shortcut menu. In the dialog box that comes up, select Bind FPGA host reference to type definition and save the control (.ctl).
2. Ensure that the control was added to the project.
3. Open the subVI, drag two of the new FPGA type definitions from the project to the front panel, and make one of the type definitions a control and the other an indicator.
4. On the block diagram, replace the current FPGA VI Reference In and FPGA VI Reference Out with the type definition control and indicator, respectively.
5. Delete the FPGA VI Reference In and FPGA VI Reference Out.
6. Reconnect the input and output terminals on the front panel of the subVI to the new type definition control and indicator.

LabVIEW 8.5:

1. Right-click the Open FPGA VI Reference VI on the host VI block diagram and select Bind to Typedef from the shortcut menu. When the Save As dialog box appears, save the control and then choose to add it to the project.
2. Open the subVI, drag two of the new FPGA type definitions from the project to the front panel, and make one of the type definitions a control and the other an indicator.
3. On the block diagram, replace the current FPGA VI Reference In and FPGA VI Reference Out with the type definition control and indicator, respectively.
4. Delete the FPGA VI Reference In and FPGA VI Reference Out.
5. Reconnect the input and output terminals on the front panel of the subVI to the new type definition control and indicator.

LabVIEW will now automatically update the type definition you created whenever changes to the Open FPGA VI Reference VI or the FPGA VI are made. LabVIEW propagates these changes within any subVIs that reference this type definition.

Additional Information

To create subVIs for reuse purposes, use the Dynamic FPGA Interface Cast primitive to cast a generic FPGA reference to a reference with specific FPGA items as seen below. This works well in tangent with the solution above to mitigate broken wire errors.