Incorrect Synthesis of Imported VHDL by Xilinx Compilation Tool for Vivado 2015.4

Updated Dec 21, 2017

Reported In


  • FPGA Xilinx Compilation Tools

Issue Details

I am importing my own VHDL into a LabVIEW 2016 FPGA design. During hardware validation testing I noticed that one of my case statements is not implemented but there were no errors during compilation. Why is this statement not implemented in the final design?


This issue is specific to the Xilinx Compilation Tool for Vivado 2015.4 included with LabVIEW 2016 FPGA Module. During synthesis, Vivado 2015.4 may incorrectly optimize out statements such as if not (variableX = variableY) in any external VHDL code. This could lead to an incorrect implementation on the FPGA hardware. 

To address this, change those particular statements to read if variableX /= variableY then in the VHDL code. Make sure the updated files get added to your LabVIEW FPGA code and recompile.


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