Solution
A Target to Host FIFO is structured such that there are two FIFOs (or buffers) that data is sent between, via a Direct Memory Access (DMA) channel.
The first buffer exists solely on the FPGA target and is configured in the project.
The second buffer exists solely on the Host. The depth of this buffer that can be requested via an Invoke Node on the Host VI.
The FPGA buffer will retain any data written to it on the FPGA VI, before it is streamed to the Host buffer via DMA. The streaming of the data via DMA happens automatically and cannot be configured in any way.
The Host buffer receives any data sent via DMA until that data is read out of the buffer in the Host VI.