Optimizing FPGA Compilation for Area or Speed

Updated Jul 23, 2018

Reported In

Hardware

  • Digital Reconfigurable I/O Device
  • Multifunction Reconfigurable I/O Device

Software

  • FPGA Xilinx Compilation Tools
  • LabVIEW Full

Issue Details

I have noticed that the LabVIEW FPGA Module Compiler optimizes the application for speed by default. How can I change this to optimize for area?

Solution

The compiler optimizes for speed as most tests require the same amount of size regardless of the optimization setting, yet may be faster when optimized for speed. If there is a particular situation where space on the FPGA device is of concern, it may be advantageous to attempt to compile with area as the optimization method.

LabVIEW 2010 or Newer
  1. Right-click Build Specifications under an FPGA target in the Project Explorer window and select New»Compilation from the shortcut menu to display the Compilation Properties dialog box. 

    Note: If an FPGA build specification already exists, you can right-click the FPGA build specification and select Properties to display the dialog box.
     
  2. Select Xilinx Options in the Category list.
  3. Uncheck the Use recommended settings box.
  4. From the Design Strategy drop-down box choose Area.
  5. Click OK.

LabVIEW 2009
  1. Right-click the FPGA target in your LabVIEW project and select Properties.
  2. Select Xilinx Options.
  3. Uncheck the Use recommended settings box.
  4. From the Design Strategy drop-down box choose Area.
  5. Click OK.

LabVIEW 8.6.x or Older

For other versions of LabVIEW, make the change manually by editing the vhdl_area.opt file. In vhdl_area.opt, locate the -opt_mode setting and change to SPEED or AREA. When compiling using a remote compile server, the vhdl_area.opt file is transferred to the the remote server, pulling the file from the development computer.


The location of the file depends on the version of LabVIEW FPGA and the FPGA target:

LabVIEW 8.6.x
 
Compile Server configuration file location for LabVIEW 8.6.x
TargetsFile Location
Spartan-3
labview\Targets\NI\FPGA\RIO\FpgaFiles\Spartan3\vhdl907x.opt
Virtex-II
labview\resource\RVI\StockIO\private\topModGenUtilities
Virtex-5
labview\Targets\NI\FPGA\RIO\FpgaFiles\Virtex5
 

LabVIEW 8.5.1 and Previous

 
Compile Server configuration file location for LabVIEW 8.5.1 and Previous
TargetsFile Path
Virtex-II
C:\NIFPGAxx\Xilinx\virtex\data
PXI-784xR 
labview\Targets\NI\FPGA\RIO\R Series\PXI-784xR\FpgaFiles 
PXI-785xR 
labview\Targets\NI\FPGA\RIO\R Series\PXI-785xR\FpgaFiles

Note: Replace xx with the version of LabVIEW FPGA Module you are using, without the decimal point (i.e. 85 for LabVIEW 8.5, etc.).

You can confirm whether a compile was optimized for area or speed by checking Optimization Goal in the Synthesis Options Summary of the Advanced compile report.

WAS THIS ARTICLE HELPFUL?

Not Helpful