IEPE C-Series Settling Behavior in DAQmx Enabled cRIOs

Updated May 13, 2019

Reported In


  • NI-9234
  • cRIO-9054
  • cRIO-9041
  • cRIO-9049

Issue Details

I'm using a DAQmx enabled cRIO with an IEPE C-Series module. When I run my program that uses the module for the first time after powering the hardware on in FPGA mode, I see the expected decaying signal or settling time . However, when I stop and run the program again, I see the decaying signal happen each time, whereas in my cDAQs or cRIOs that are not DAQmx enabled, the decaying signal only happens once after powering the hardware on. Why is this?


DAQmx-enabled CompactRIO controllers have additional initialization requirements due to the hardware that enables DAQmx functionality. These initialization steps cause this decaying behavior to occur every time the FPGA is reset. Note that manually resetting the module in NI MAX will not cause this to occur. 

Check in your code to see if you're resetting the FPGA each time the code runs. It is possible to avoid this settling time by ensuring the following:
  • The bitfile is only downloaded if necessary (changes have been made).
  • Only changing the module configuration if needed between runs, including IEPE settings.
  • Avoid resetting the FPGA at the start of each run.