Can the Sample Rate of the PXIe-5785 Analog Input Channel Be Modified?

Updated Nov 30, 2023

Reported In

Hardware

  • PXIe-5785

Issue Details

I use the example Basic. vi, the Sample Rate of the analog input AI in the example project is not adjustable and set to 3.2Gsps.

Solution

If you do not change the FPGA code,the AI ​​and AO sample rate of the PXIe-5785 board can not adjust.
  • If you set the ADC Interleaving Factor parameter to 1,indicates that the sampe rate of the ADC is 3.2 GS/s.
  • If you set the ADC Interleaving Factor parameter to 2,indicates that the sampe rate of the ADC is 6.4 GS/s.
However, it is possible to do some processing on the FPGA side by using the method of decimation, which is equivalent to changing the sampling rate.

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