Error 65582 with NI 922x or NI 923x in FPGA

Updated Mar 29, 2019

Reported In

Hardware

  • CompactRIO Chassis
  • CompactRIO Controller
  • NI-9231
  • NI-9232
  • NI-9234
  • NI-9235
  • NI-9236
  • NI-9237
  • NI-9238
  • NI-9239
  • NI-9225
  • NI-9227
  • NI-9229

Software

  • LabVIEW FPGA Module

Driver

  • NI CompactRIO

Issue Details

I am using a C Series module with a Delta-Sigma ADC like a NI 9234 to acquire analog signals using the FPGA in my CompactRIO. When I try to perform the acquisition, I get the following error.

Error 65582 occurred at an unidentified location

CompactRIO: (Hex 0x1002E) The operation did not complete because the acquisition has not started. Use the Start and Stop channels to put the module in and out of acquisition mode.

Solution

The error is caused because the acquisition is not being started by using the FPGA I/O Node ModX/Start (where X is the number of the module). You need to wire a True boolean constant in the input ModX/Start of this node.
 
 

It is also required to use the FPGA I/O Node ModX/Stop (where X is the number of the module) at the end of the operation. You need to wire a True boolean constant in the input ModX/Stop of this node.
 

These nodes are located in the Project Explorer window by expanding RT CompactRIO Target >> Chassis >> FPGA Target >> ModX.  They can be placed in the block diagram by simply dragging them from the project explorer onto the block diagram.

Additional Information

Refer to C Series Device Groupings in the NI-DAQmx Help if you are unsure if you have a Delta-Sigma module.

This error can also show up if you have multiple modules being started in parallel and read at the same time. If you are acquiring multiple modules, start all of them in a single FPGA IO Node.
In order to optimize performance it is best to start and stop Delta-Sigma modules outside the while loop used to acquire data. The LabVIEW snippet below shows how to do this assuming that you set the coupling parameters from the property menus in the project explorer. Download and drag the snippet into a new VI block diagram to generate the code or download the attached FPGA IO Node Loop Time Acquire.vi.
 

You can also programmatically set the coupling type and other properties if needed. To learn more about configuring Delta-Sigma modules programmatically, refer to the corresponding NI 92xx Getting Started.lvproj shipping example in the Example Finder.

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