Hardware I/O Latency Times in NI VeriStand

Updated Aug 2, 2018

Reported In

Software

  • VeriStand

Issue Details

I have an NI VeriStand real-time system. I will be acquiring from hardware (either DAQ or FPGA), processing it in my model, and then outputting data. What latency should I expect between hardware input and output, and what can I do to reduce this latency?

Solution

Hardware input and output latency depends on the execution mode specified in the System Definition. On the Controller page in the System Explorer, you can choose either Parallel execution mode or Low Latency execution mode. The following behavior applies to both DAQ and FPGA hardware input/output in these execution modes:

Parallel Execution (DAQ and FPGA - default)

  1. First loop cycle - hardware input is acquired and passed to the model.
  2. Second loop cycle - the model processes the acquired data and generates the output data. This data is sent to the output buffer, but not generated yet.
  3. Third loop cycle - hardware output is generated.
Thus, there is a two tick delay from input to output.

Low Latency Execution (DAQ and FPGA - default)

  1. First loop cycle - hardware input is acquired and passed to the model. The model processes the acquired data and generates output data. This data is sent to the output buffer, but not generated yet.
  2. Second loop cycle - hardware output is generated.
Thus, there is a single tick delay from input to output.

For DAQ hardware, input and output tasks use the same hardware sample clock, so it is necessary to wait for the next tick to update the output signal. FPGA tasks, on the other hand, use Feedback Nodes to cause the data to be written to the output with hardware timing. These Feedback Nodes can be removed, and thus the output signal would be generated within the same loop iteration. However, doing this will cause the FPGA IO output to not be hardware-timed. This will cause more jitter in the code, so keep in mind that this method sacrifices some determinism. The following behavior applies in this case:

Parallel Execution (FPGA - without hardware timing)

  1. First loop cycle - hardware input is acquired and passed to the model.
  2. Second loop cycle - the model processes the acquired data and generates output data. This data is sent to the output buffer and generated by the hardware.
Thus, there is a single tick delay plus approximately the High Priority (HP) Loop duration from input to output.

Low Latency Execution (FPGA - without hardware timing)

  1. First loop cycle - hardware input is acquired and passed to the model. The model processes the acquired data and generates output data. This data is sent to the output buffer and generated by the hardware.
Thus, there is a delay of approximately the HP Loop duration from input to output. The HP loop duration will be longer in this scenario than in the parallel execution setting, because HP loop duration includes the model execution time.

Additional Information

There is a trade-off to choosing a low-latency execution setting. This setting can minimize latency and CPU usage, but can also significantly slow the execution speed of the system. Choose parallel execution to increase execution speed.
 

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