5751 and 5752 NI FlexRIO Adapter Module Synchronization

Updated Aug 16, 2018

Reported In

Hardware

  • NI-5751
  • NI-5752

Issue Details

I would like to perform synchronization of multiple 5751 or 5752 NI FlexRIO adapter modules. What is required to perform this synchronization, and which versions of LabVIEW are compatible with my NI FlexRIO FPGA modules?

Solution

Synchronization of the 5751 or 5752 NI FlexRIO adapter modules requires PXI Express NI FlexRIO modules, which require LabVIEW 2009** or later. PXIe NI FlexRIO FPGA modules are necessary as synchronization requires the use of the DStar lines on the backplane. Additionally, a PXIe Timing and Synchronization (T&S) module is required to drive the DSTARA and DSTARB lines with a common sample clock and trigger signal. 

A synchronous clock can be sent to each module across the DSTARA backplane lines with limited skew by using a T&S module such as the PXIe-6674. This device can also send a divided-down version of the sample clock across the DSTARB lines to be used for triggering purposes. This method is necessary for triggering since a start trigger is generally sent from the master on a falling edge of the sample clock and must be received by all of the slave devices before the next rising edge of the sample clock (only half a sample clock period later), which is not guaranteed. By using a slower signal which is synchronous to the sample clock, the trigger can be sent from the master device on a falling edge of the DSTARB clock, and the slave devices will have more time to receive the trigger before the next rising edge of the DSTARB clock. 

A special CLIP version is available for both the 5751 and 5752 to accomplish synchronization in this manner. 

Additional Information

**For LabVIEW 2009 support, the attached VI must be substituted due to incorrect timing constraints for DSTARA found in LabVIEW 2009. The file "nirviGenPeriodConstraint.vi" should be replaced in the following location within the LabVIEW 2009 directory: 

...\<National Instruments>\LabVIEW 2009\vi.lib\rvi\ClientSDK\Core\TimingSources\Generation\Public\nirviGenPeriodConstraint.vi 

This issue has been resolved in later versions of LabVIEW. Substituting the VI below is not necessary for these versions. Please see LabVIEW FPGA 2009 Does Not Generate Period Constraints for PXI_DSTARA for more information on this issue.

 

WAS THIS ARTICLE HELPFUL?

Not Helpful