Solution
Synchronization of the 5751 or 5752 NI FlexRIO adapter modules requires PXI Express NI FlexRIO modules, which require LabVIEW 2009** or later. PXIe NI FlexRIO FPGA modules are necessary as synchronization requires the use of the DStar lines on the backplane. Additionally, a PXIe Timing and Synchronization (T&S) module is required to drive the DSTARA and DSTARB lines with a common sample clock and trigger signal.
A synchronous clock can be sent to each module across the DSTARA backplane lines with limited skew by using a T&S module such as the PXIe-6674. This device can also send a divided-down version of the sample clock across the DSTARB lines to be used for triggering purposes. This method is necessary for triggering since a start trigger is generally sent from the master on a falling edge of the sample clock and must be received by all of the slave devices before the next rising edge of the sample clock (only half a sample clock period later), which is not guaranteed. By using a slower signal which is synchronous to the sample clock, the trigger can be sent from the master device on a falling edge of the DSTARB clock, and the slave devices will have more time to receive the trigger before the next rising edge of the DSTARB clock.
A special
CLIP version is available for both the 5751 and 5752 to accomplish synchronization in this manner.