How Many FPGA Clock Ticks Will My Analog Input or Output Node Require?

Updated Aug 13, 2019

Reported In


  • CompactRIO Chassis


  • LabVIEW
  • LabVIEW FPGA Module

Issue Details

I am working with a C Series module or R Series FPGA board with analog inputs and outputs. The I/O Nodes for each device requires a deterministic number of clock ticks, but that number differs for each device based on its sampling rate. Is there a way to determine how many clock ticks each device will take?


There are a number of factors that determine how many clock ticks a particular I/O Node will require, including the sampling rate of the device, the top-level FPGA clock being used, and even the version of the driver. Because of these variables, there is not simply a table listing the number of clock ticks needed by each device. The best way to determine this value is to benchmark it with a simple FPGA VI . You can do this with each of your devices, and the value should remain constant unless you change LabVIEW or driver versions, or your top-level clock rate.