There are a number of factors that determine how many clock ticks a particular I/O Node will require, including the sampling rate of the device, the top-level FPGA clock being used, and even the version of the driver. Because of these variables, there is not simply a table listing the number of clock ticks needed by each device. The best way to determine this value is to benchmark it with a simple FPGA VI
. You can do this with each of your devices, and the value should remain constant unless you change LabVIEW or driver versions, or your top-level clock rate.