Update Rate of Counter Frequency Task in VeriStand

Updated Jul 23, 2018

Reported In


  • VeriStand

Issue Details

My counter frequency task in VeriStand is not updating at the rate that I expect. Why is this happening? 


The update rate of frequency task is the lower limit of the channel frequency. If this is set to 1Hz then the update rate will be 1Hz.  

The way that the frequency task is working in VeriStand is that the VeriStand engine calculates the frequency by counting the number of pulses between ticks of the Primary Control Loop. Thus, the accuracy of this calculation will be tied directly to the jitter of the PCL. For example, if you measure the PCL and determine a 5% deviation, we can expect a 5% error in the frequency measurement. This method is software timed and because of this it is subject to bad performance.

It is recommended to use a Pulse Measurement task instead. This task is an option if using one of our X series devices. Another option is to use an R series device and implement the frequency measurement on the FPGA. 


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