How Are PXI_CLK10 and PXIe_CLK100 Related?

Updated Jan 15, 2019

Reported In

Hardware

  • PXI Chassis

Issue Details

I have a PXIe chassis that has PXI_CLK10 and PXIe_CLK100 system reference clocks. Some of the modules I have in my chassis only synchronize to PXI_CLK10 and some only synchronize to PXIe_CLK100. How are these two system reference clocks related? Is there a way to synchronize all my modules together?

Solution

PXI_CLK10 is generated from PXIe_CLK100. They are phase lock looped (PLL) together. The PXI_CLK10 and PXIe_CLK100 have the following default timing relationship:



As shown in the above default timing relationship, there may be up to 6.5 ns of skew between PXI_Clk10 and PXIe_Clk100. However, this delay is constant due to PXI_Clk10 and PXIe_Clk100 being PLL together so you can synchronize all modules in your PXIe chassis. For more information on using reference clock synchronization please see the White Paper article Synchronization Explained.

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