Error -61161 Execution Mode Not Supported Outside Single-Cycle Timed Loop

Updated Aug 14, 2018

Reported In


  • LabVIEW FPGA Module

Issue Details

I am trying to deploy a VI to my FPGA but am getting error -61161 VI Execution Mode not supported outside single-cycle Timed Loop.


Some express VI's, including those from the High Throughput Math Functions pallet, offer the ability to select an execution mode. This error occurs when the execution mode is set to 'Inside single-cycle Timed Loop' but the function is being called outside of a single-cycle timed loop.

To fix this issue, double click any express VI's that are outside of single-cycle timed loop and change the execution mode to Outside single-cycle Timed Loop.


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