Synchronising NI Waveform Generator with External Clock

Updated Sep 10, 2018

Reported In

Hardware

  • PXIe-5442

Software

  • LabVIEW 2017 Full

Driver

  • NI-FGEN 17.1

Issue Details

I have an external variable clock source and would like to synchronize my function generator with it. How can I do this and what delays can I expect ?

Solution

There are two ways to use an external clock to set the sample clock of an NI Waveform Generator card.

Reference Clock Synchronization :
  1. External Clock is routed to on board PLL circuit through PFI connector on the Waveform generator front panel. This is used as reference to generate the sample clock used by the card.
  2. This is implemented in LabVIEW using the niFgen Configure Reference Clock VI.
  3. Reference clock frequency can only take certain values mentioned in the specification sheet. The generated clock is synchronized in frequency with external clock.
  4. The generated clock has a constant phase difference with external clock which is expected with a PLL circuit. However, this phase difference is:
    1. Variable across runs with the same setup if generation is not triggered by the external clock. The delay is caused by PLL locking time which is variable and is estimated in the specification sheet.
    2. Constant though multiple runs with the same setup if generation is triggered by the external clock. This delay is caused by the circuitry between the trigger input terminal and generation terminal. It is also dependent on sample clock frequency and is estimated in the specification sheet.

External Sample Clock Synchronization :
  1. External clock is routed directly to the waveform generation engine and DAC. There is no PLL circuit in between and the card uses the external clock directly as the sample clock. No new clock is generated.
  2. This is Implemented in LabVIEW using the niFGen Configure Sample Clock Source VI followed by niFGen Set Sample Rate VI.
  3. A constant phase difference between the external clock and sample clock is still present. This delay is caused by the circuitry between the sample clock input terminal and the generation terminal.
  4. The behavior is such, irrespective of whether triggering has been used or not.
  5. This clock mode allows only arbitrary waveform or arbitrary sequence mode.
Examples demonstrating these features are present in the example finder in the Hardware Input and Output -> Modular Instruments -> NI-FGEN folder.

 

Additional Information

  • Clocking diagrams of various waveform generator cards such as for the PXIe-5442 card are present in NI Signal Generators help document under the devices section and are helpful in understanding signal paths.
  • The niFgen Adjust Sample Clock Relative Delay VI can be used to offset the clock by a certain amount. This can help in elimination of the constant phase delays if any.

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