What is the Difference Between Sample Rate and I/Q Rate on NI RF Devices?

Issue Details

• What is the difference between sample rate and I/Q rate on NI RF devices? 
• How can I adjust the I/Q rate if RF devices have a fixed sample rate?  

Solution

The I/Q sample rate on an RF device seen from the specifications relates to the rate at which the ADCs and DACs run. This I/Q sampling rate on RF instruments is often a fixed rate, meaning the ADC or DAC is always converting the data at this rate. The fixed sampling rate for the ADCs and DACs helps to avoid aliasing of the signal prevent loss of data. On the RX side, once the data is sampled by the ADC at the fixed rate, the data is then decimated to the user-defined IQ rate via digital downconverters in the FPGA. On the TX side, the signal data based on the user-defined IQ rate is sent through digital upconverters in the FPGA where the signal is interpolated to the fixed DAC rate and then sent to the DAC to be converted to an analog signal.
 
The method of how the signal data is translated to I and Q data depends on the architecture of the RF instrument. For example, the USRP-2954 uses a direct conversion architecture which utilizes quadrature mixers to downconvert or upconvert the signal into it's individual in-phase (I) and quadrature (Q) components. For the direct conversion architecture, there are dedicated ADCs and DACs for each I and Q branch which send the data to/from the FPGA. The USRP-2955 and USRP-X410 use a multi-stage superheterodyne architecture where the incoming signal goes through multiple stages of conditioning and downconversions which then gets sampled by the ADC at the fixed rate. The output of the digitized signal is passed into the FPGA where it goes through the digital downconverter which decimates the signal into the I and Q data at the user specified rate.
 
Overall, the sampling rate is based off of the ADC or DAC conversion rate. The I/Q rate is the user-defined data rate which is accomplished by digital downconversion or digital upconversion in the FPGA.


IQ rate also affects bandwidth of a device. Due to filter roll off, it is good practice to set your IQ rate and bandwidth to not exceed the following limitation:
 
Filter roll off will causes data on the ends of the specified bandwidth to appear distorted.  Because of this, following the above equation is good programming practice.

For additional information on aliasing, bandwidth, and sampling, refer to the following white paper Acquiring an Analog Signal: Bandwidth, Nyquist Sampling Theorem, and Aliasing

Additional Information

It is also worthwhile to point out how setting your IQ rate can affect your program. Data is saved onboard the USRP, and then a fetch is used to send this data from the USRP to the host. If data is not managed appropriately, you can run into an underflow or overflow error. An underflow error occurs if there is not data available on the USRP memory to send to the host, but the host tries to fetch data. An overflow error occurs if data is not sent to the host quickly enough to keep up with data being stored on USRP memory. This causes memory to be overwritten.