The pins specified as "Routed to FPGA Global Clock Resources on the Host System" feed directly into the FPGA's clocking system.
In other words, these pins were designed for properly importing external clocks into the FPGA of the sbRIO. They can distribute the clock among the entire FPGA o among the resources of a specific region in a way that doesn't generate skew or timing differences between code/loops that use the same clock.
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