What Are Pins Routed to FPGA Global Clock in the SbRIO-9607?

Updated Jun 1, 2018

Reported In

Hardware

  • sbRIO-9607

Issue Details

In the User Manual of sbRIO-9607 at the RMC (RIO Mezzanine Card) Connector pin listing, some pins are defined as Routed to FPGA Global Clock Resources on the Host System, what is the function of this pins?

Solution

The pins specified as "Routed to FPGA Global Clock Resources on the Host System" feed directly into the FPGA's clocking system.

In other words, these pins were designed for properly importing external clocks into the FPGA of the sbRIO. They can distribute the clock among the entire FPGA o among the resources of a specific region in a way that doesn't generate skew or timing differences between code/loops that use the same clock.

Additional Information

Component-Level IP (CLIP) has to be used when importing external clocks into the FPGA. Also, these DIO lines can also be used as general purpose DIO lines.

For further details about the Component-Level Intellectual Property see the document Importing External IP Into LabVIEW FPGA.

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