Additional Information
The sample rate is limited by the hardware Analog-to-Digital Converter (ADC). The upper limit of this converter is, in the myRIO-1900's and myRIO-1950's case, 500 kS/s.
The Field-Programmable Gate Array (FPGA) is connected to the Analog Input (AI) pins through the ADC, as can be seen in the
NI myRIO-1900 Block Diagram (myRIO Module). This is reasonable, as the analog signal has to be converted before it can be used in digital circuitry. Because of this the ADC's speed is the limiting factor of the sampling rate, irrespective of the FPGA's performance.