The HDL Interface Node is a configurable VI that allows you to integrate VHDL code into your LabVIEW FPGA VI. The API resembles the Call Library Function Node. You can type your VHDL code directly into the Configure HDL Interface Node dialog box. You also can specify .vhd files in the Configure HDL Interface Node dialog box. Refer to the tutorial Importing HDL Code into FPGA VIs Using the HDL Interface Node. NOTE : The HDL Interface Node is deprecated and has been replaced with the IP Integration node since LabVIEW 2010.
The functionality is same as the HDL Interface Node. Refer to Importing External IP Into LabVIEW FPGA(section 3) for more information on using it.
Use CLIP for parallel execution of your HDL code in the LabVIEW FPGA. Refer to Importing External IP Into LabVIEW FPGA(section1) to understand more about the CLIP. The same article discusses the difference between a CLIP and IP Integration node. The CLIP Tutorial shows the steps involved in creating a CLIP in detail.
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