Issue Details

Solution

Yes, you can import your VHDL or Verilog into the LabVIEW FPGA VI in the following ways :
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• HDL Interface Node(deprecated) :

  The HDL Interface Node is a configurable VI that allows you to integrate VHDL code into your LabVIEW FPGA VI. The API resembles the Call Library Function Node. You can type your VHDL code directly into the Configure HDL Interface Node dialog box. You also can specify .vhd files in the Configure HDL Interface Node dialog box.​ Refer to the tutorial Importing HDL Code into FPGA VIs Using the HDL Interface Node .
  
  NOTE : The HDL Interface Node is deprecated and has been replaced with the IP Integration node since LabVIEW 2010.

• IP Integration Node :

  The functionality is same as the HDL Interface Node. Refer to Importing External IP Into LabVIEW FPGA(section 3)  for more information on using it.

• Component Level Intellectual Property(CLIP) :

  Use CLIP for parallel execution of your HDL code in the LabVIEW FPGA. Refer to Importing External IP Into LabVIEW FPGA(section1)  to understand more about the CLIP. The same article discusses the difference between a CLIP and IP Integration node. The CLIP Tutorial shows the steps involved in creating a CLIP in detail.

Additional Information

• Edit your existing VHDL-2008 code to be in the correct syntax.
• Synthesize your existing code into a netlist that can then be loaded into LabVIEW FPGA. Please note that the Xilinx Vivado Design Suite and compilation tools may not support all features of VHDL-2008. Please refer to the Vivado Design Suite User Guide - Synthesis for more information about which subset of VHDL-2008 is supported.