RFSA PLL Could Not Phase Lock to External Reference Clock

Updated May 29, 2025

Reported In

Hardware

  • PXI-5661

Issue Details

When trying to open the RFSA Soft Front Panel to use my vector signal analyzer, I receive an error:

Error -223552: PLL could not phase lock to external reference clock; ensure that it is within jitter and phase specifications

Why do I see this error, and how can I correct it?

Solution

This error is commonly a result of incorrect cabling of the VSA. In the case of the PXI-5661, incorrectly connecting the 10 MHz PXI clock signal, as noted in the Getting Started Guide, can cause this error. 

Ensure that all necessary connections are made with working cables on your modules to proceed.

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