Auto-Indexing While Loop Not Allowed in FPGA Module

Updated Jul 2, 2018

Reported In


  • LabVIEW FPGA Module

Issue Details

I am  trying to build a LV FPGA code and I am coming across an error stating " The While Loop contains an auto-indexed output tunnel. The FPGA Module does not support auto-indexed output tunnels on the While Loop."



Auto-indexing in while loops creates an issue with FPGA code because the FPGA does not know how much space in memory is needed to complete the task. Some recommendations are as follows:

Auto-Index a For Loop: The For Loop already has a set number of iterations and has that memory space preallocated for the FPGA code. This will not only prevent that message from popping up, but can help reduce the amount of resources you are using on the FPGA code.

Analyze Data in the While Loop: Doing all functionality within the While Loop will minimize the amount of resources the FPGA uses and will still keep the code running. 

Additional Information

For more information about optimizing FPGA code follow this link here.



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