I am trying to build a LV FPGA code and I am coming across an error stating " The While Loop contains an auto-indexed output tunnel. The FPGA Module does not support auto-indexed output tunnels on the While Loop."
Thank you for your feedback.
You changed your response to Not Helpful
You changed your response to Helpful
Collaborate with other users in our discussion forums
A valid service agreement may be required, and support options vary by country.