Solution
To integrate IP whose top-level VHDL file contains other data types, you must:
- Create a wrapper VHDL file that converts all port types to std_logic and std_logic_vector. For more information on the conversion functions to use, refer to the tables below.
- Add both the original VHDL and wrapper VHDL file to the list of synthesis files the IP Integration Node uses.
- Specify the wrapper VHDL file as the top-level synthesis file.
National Instruments recommends that you use the conversion functions in the
ieee.std_logic_1164 and
ieee.numeric_std libraries. The following tables show some typical conversions that use these libraries:
From/To | std_logic | std_logic_vector |
signed | - | std_logic_vector (from) |
unsigned | - | std_logic_vector (from) |
bit | to_stdulogic (from) | - |
bit_vector | | std_logic_vector (unsigned(from)) |
boolean | '1' when from else '0' | - |
integer | - | std_logic_vector (to_signed (from, size)) |
To/From | std_logic | std_logic_vector |
signed | - | signed (from) |
unsigned | - | unsigned (from) |
bit | to_bit (from) | - |
bit_vector | - | to_bitvector (from) |
boolean | true when from='1' else false | - |
integer | - | to_integer (signed (from)) |