Use Other VHDL Data Types with the LabVIEW FPGA IP Integration Node

Updated Apr 3, 2023

Reported In

Software

  • LabVIEW FPGA Module

Issue Details

The LabVIEW FPGA IP Integration Node supports only the std_logic and std_logic_vector data types for top-level VHDL files. How can I use the IP Integration Node with other signal types? 

Solution

To integrate IP whose top-level VHDL file contains other data types, you must: 
  1. Create a wrapper VHDL file that converts all port types to std_logic and std_logic_vector. For more information on the conversion functions to use, refer to the tables below. 
  2. Add both the original VHDL and wrapper VHDL file to the list of synthesis files the IP Integration Node uses. 
  3. Specify the wrapper VHDL file as the top-level synthesis file. 

National Instruments recommends that you use the conversion functions in the ieee.std_logic_1164 and ieee.numeric_std libraries. The following tables show some typical conversions that use these libraries: 
 

  • From other data type to std_logic or std_logic_vector:

From/Tostd_logicstd_logic_vector
signed-std_logic_vector (from)
unsigned-std_logic_vector (from)
bitto_stdulogic (from)-
bit_vector std_logic_vector (unsigned(from)) 
boolean'1' when from else '0'-
integer-std_logic_vector (to_signed (from, size))

 

  • To other data type from std_logic or std_logic_vector:

To/Fromstd_logicstd_logic_vector
signed-signed (from)
unsigned-unsigned (from)
bitto_bit (from)-
bit_vector-to_bitvector (from)
booleantrue when from='1' else false-
integer-to_integer (signed (from))

Additional Information

As an example, the MultiplyAdder.zip file attached to this KnowledgeBase article contains two example .vhd files:
  • MultiplyAdder.vhd is the original top-level VHDL file that contains signed, unsigned, integer, bit, and Boolean data types. 
  • MultiplyAdderWrapper.vhd is the wrapper file that converts these data types to std_logic and std_logic_vector. This must be the top-level synthesis file.

Attachments

MultiplyAdder.zip

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