Error -50400 at DMA FIFO Read on LabVIEW Real-Time or Host Program

Issue Details

Solution

• The FIFO is not getting written to. This might happen because you aren't actually acquiring data, or updating data in your FPGA program. You can check if data is properly received by wiring indicators to the inputs of your FIFO Write in the FPGA program. You can also monitor the Timed Out? boolean to see if it timed out before the FIFO was written to. 

• The host program is timing out before the FPGA program has a chance to write to the FIFO. Increase the timeout of the FIFO Read method on your host program.

• It could be that your FPGA program is not running. Confirm and/or run your FPGA program.
• If you only get this error when you stop the host VI, and are manually stopping the FPGA VI using a read/write control in the Host VI main loop, make sure that you stop the FPGA VI after the Read method executes rather than before. Alternatively, you can simply use the "Close FPGA VI Reference.vi" to close and reset the FPGA VI, as the last step when the host VI stops.