SampleClkSrcSelect Inside Case Structure Executes Unexpectedly

Updated May 25, 2018

Reported In


  • PXIe-7961
  • NI-5752
  • FlexRIO Digitizer Device
  • PXI FlexRIO Digitizer
  • PXI FPGA Module for FlexRIO


  • LabVIEW
  • LabVIEW FPGA Module

Issue Details

I am trying to set the clock for my FlexRIO device using the SampleClkSrcSelect property from an FPGA I/O node, by placing the node inside a case structure. However, the program ignores the case structure and sets the clock for my device when I update the clock from my front panel, regardless of the case that is set to execute in the case structure. Is there some way of using the case structure to configure when the clock for my device is set?


This is a known issue but there is a workaround for it. You can still implement the case structure to configure when the clock is set for your device by placing the FPGA I/O node inside a single cycle timed loop and using a shift register instead of a tunnel for the input to the property node.


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